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NXP Semiconductors
PCA9626
24-bit Fm+ I 2 C-bus 100 mA 40 V LED driver
7.3.4 GRPPWM, group duty cycle control
Table 8. GRPPWM - Group brightness control register (address 1Ah) bit description
Legend: * default value
Address
1Ah
Register
GRPPWM
Bit
7:0
Symbol
GDC[7:0]
Access
R/W
Value
1111 1111
Description
GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed
frequency signal is superimposed with the 97 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LED outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from
24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
GDC ? 7 : 0 ?
duty cycle = --------------------------
256
7.3.5 GRPFREQ, group frequency
Table 9. GRPFREQ - Group Frequency register (address 1Bh) bit description
Legend: * default value.
(2)
Address
1Bh
Register
GRPFREQ
Bit
7:0
Symbol
GFRQ[7:0]
Access
R/W
Value
0000 0000*
Description
GRPFREQ register
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5
registers).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73 s).
global blinking period = ---------------------------------------- ? s ?
GFRQ ? 7 : 0 ? + 1
24
(3)
PCA9626
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 September 2012
? NXP B.V. 2012. All rights reserved.
13 of 47
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